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(R)
STA015 STA015B STA015T
MPEG 2.5 LAYER III AUDIO DECODER WITH ADPCM CAPABILITY
PRODUCT PREVIEW
SINGLE CHIP MPEG2 LAYER 3 DECODER SUPPORTING: - All features specified for Layer III in ISO/IEC 11172-3 (MPEG 1 Audio) - All features specified for Layer III in ISO/IEC 13818-3.2 (MPEG 2 Audio) - Lower sampling frequencies syntax extension, (not specified by ISO) called MPEG 2.5 DECODES LAYER III STEREO CHANNELS, DUAL CHANNEL, SINGLE CHANNEL (MONO) SUPPORTING ALL THE MPEG 1 & 2 SAMPLING FREQUENCIES AND THE EXTENSION TO MPEG 2.5: 48, 44.1, 32, 24, 22.05, 16, 12, 11. 025, 8 KHz ACCEPTS MPEG 2.5 LAYER III ELEMENTARY COMPRESSED BITSTREAM WITH DATA RATE FROM 8 Kbit/s UP TO 320 Kbit/s ADPCM CODEC CAPABILITIES: - sample frequency from 8 kHz to 32 kHz - sample size from 8 bits to 32 bits - encodingalgorithm: DVI, ITU-G726pack (G723-24,G721,G723-40) - Tone controlandfast-forward capability EASY PROGRAMMABLE GPSO INTERFACE FOR ENCODED DATA UP TO 5Mbit/s (TQFP44 & LFBGA 64) DIGITAL VOLUME BASS & TREBLE CONTROL SERIAL BITSTREAM INPUT INTERFACE EASY PROGRAMMABLE ADC INPUT INTERFACE ANCILLARY DATA EXTRACTION VIA I2C INTERFACE. SERIAL PCM OUTPUT INTERFACE (I2S AND OTHER FORMATS) PLL FOR INTERNAL CLOCK AND FOR OUTPUT PCM CLOCK GENERATION CRC CHECK AND SYNCHRONISATION ERROR DETECTION WITH SOFTWARE INDICATORS I2C CONTROL BUS LOW POWER 2.4V CMOS TECHNOLOGY WIDE RANGE OF EXTERNAL CRYSTALS FREQUENCIES SUPPORTED
ORDERING NUMBERS: STA015 (SO28) STA015T (TQFP44) STA015B (LFBGA 64)
APPLICATIONS PC SOUND CARDS MULTIMEDIA PLAYERS VOICE RECORDERED DESCRIPTION The STA015 is a fully integrated high flexibility MPEG Layer III Audio Decoder, capable of decoding Layer III compressed elementary streams, as specified in MPEG 1 and MPEG 2 ISO standards. The device decodes also elementarystreams compressed by using low sampling rates, as specified by MPEG 2.5. STA015 receives the input data through a Serial Input Interface. The decoded signal is a stereo, mono, or dual channel digital output that can be sent directly to a D/A converter, by the PCM Output Interface. This interface is software programmable to adapt the STA015 digital output to the most common DACs architectures used on the market. The functional STA015 chip partitioning is described in Fig.1 and Fig.2.
February 2000
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
STA015-STA015B-STA015T
Figure 1a. BLOCK DIAGRAM for TQFP44 and LFBGA64 package
SDA 31
SCL 32
TQFP44
I C CONTROL 34 SDI SCKR BIT_EN 36 38 SERIAL INPUT INTERFACE DSP BASED 42 BUFFER 256 x 8 MPEG L III ADPCM CORE VOLUME & TONE CONTROL OUTPUT BUFFER PCM OUTPUT INTERFACE 44 2 3
2
GPIO INTERFACE
SDO SCKT LRCKT OCLK
DATA-REQ
27
PARSER
40 SCK_ADC CRCK_ADC SDI_ADC 26 24 ADC INPUT INTERFACE
4 SYSTEM & AUDIO CLOCKS GPSO INTERFACE 28 33 25 RESET 15 XTI 13 XTO 22 TESTEN 12 FILT
D99AU1116
GPSO_REQ GPSO_SCKL GPSO_DATA
Figure 1b. BLOCK DIAGRAM for SO28 package
SDA 3
SCL 4
SO28
I C CONTROL 5 6 7 SERIAL INPUT INTERFACE
2
SDI SCKR BIT_EN
DSP BASED 9 BUFFER 256 x 8 MPEG L III ADPCM CORE VOLUME & TONE CONTROL OUTPUT BUFFER PCM OUTPUT INTERFACE 10 11 12
SDO SCKT LRCKT OCLK
DATA-REQ
28
PARSER
SCK_ADC CRCK_ADC SDI_ADC
8 27 25 ADC INPUT INTERFACE
SYSTEM & AUDIO CLOCKS
26 RESET
21 XTI
20 XTO
24 TESTEN
19 FILT
D99AU1117
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STA015-STA015B-STA015T
Figure 2. PIN CONNECTIONS
VDD_1 VSS_1 SDA SCL SDI SCKR BIT_EN SRC_INT/SCK_ADC SDO SCKT LRCKT OCLK VSS_2 VDD_2 1 2 3 4 5 6 7 8 9 10 11 12 13 14
D99AU1061
28 27 26 25 24 23 22
OUT_CLK/DATA_REQ LRCK_ADC RESET SDI_ADC TESTEN VDD_4 VSS_4 XTI XTO FILT PVSS PVDD VDD_3 VSS_3
SO28
21 20 19 18 17 16 15
SRC_INT/SCK_ADC
GPIO/STROBE
35
IODATA[7]
IODATA[6]
IODATA[5]
IODATA[4]
BIT_EN
SCKR
SCKT
SDO
44
43
42
41
40
39
38
37
36
34 33 32 31 30 29
N.C. LRCKT OCLK GPSO_REQ VSS_2 VDD_2 VSS_3 VDD_3 N.C. PVDD PVSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
SDI
GPSO_DATA SCL SDA VSS_1 VDD_1 GPSO_SCKR OUT_CLK/DATA_REC LRCK_ADC RESET SDI_ADC N.C.
TQFP44
28 27 26 25 24 23
XTI
VSS_4
N.C.
IODATA[3]
IODATA[2]
IODATA[1]
IODATA[0]
VDD_4
FILT
XTO
TESTEN
D99AU1062
8 A B C D E F G H
7
6
5
4
3
2
1 A1 = SDI B2 = SCKR D4 = BIT_EN D1 = SRC_INT E2 = SDO F2 = SCKT H1 = LRCKT H3 = OCLK F3 = VSS_2 E4 = VDD_2 G4 = VSS_3 G5 = VDD_3 F5 = PVDD G6 = PVSS G7 = FILT G8 = XTO F7 = XTI E7 = VSS_4 C8 = VDD_4 D7 = TESTEN A7 = SDI_ADC B6 = RESET A5 = LRCK_ADC C5 = OUT_CLK/DATA_REQ B5 = VDD_1 B4 = VSS_1 A4 = SDA B3 = SCL C2 = GPIO_STROBE C3 = IODATA [4] E3 = IODATA [5] D2 = IODATA [6] F1 = IODATA [7] G3 = GPSO_REQ F8 = IODATA [3] F6 = IODATA [2] E6 = IODATA [1] C7 = IODATA [0] C6 = GPSO_SCKR A2 = GPSO_DATA
D00AU1149
LFBGA64
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STA015-STA015B-STA015T
1. OVERVIEW 1.1 - MP3 decoder engine The MP3 decoder engine is able to decode any Layer III compliant bitstream: MPEG1, MPEG2 and MPEG2.5 streams are supported. Besides audio data decoding the MP3 engine also performs ANCILLARY data extraction: these data can be retrieved via I2C bus by the application microcontroller in order to implement specific functions. Decoded audio data goes through a software volume control and a two-band equalizer blocks before feeding the output I2S interface. This results in no need for an external audio processor. MP3 bitstream is sent to the decoder using a simple serial input interface (see pins SDI, SCKR, BIT_EN and DATA_REQ), supporting input rate up to 20 Mbit/s. Received data are stored in a 256 bytes long input buffer which provides a
feedback line (see DATA_REQ pin) to the bitstream source (tipically an MCU). 1.2 - ADPCM encoder/decoder engine This device also embeds a multistandard ADPCM encoder/decoder supporting different sample rates (from 8 KHz up to 32 KHz) and different sample sizes (from 8 bit to 32 bits). During encoding process two different interfaces can be used to feed data: the serial input interface (same interface used also to feed MP3 bitstream) or the ADC input interface, which provides a seamless connection with an external A/D converter. The currently used interface is selected via I2C bus. Also to retrieve encoded data two different interfaces are available: the I2C bus or the faster GPSO output interface. GPSO interface is able to output data with a bitrate up to 5 Mbit/s and its control pins (GPSO_SCKR, GPSO_DATA and GPSO_REQ) can be configured in order to easily fit the target application.
ABSOLUTE MAXIMUM RATINGS
Symbol VDD Vi VO Tstg Toper Power Supply Voltage on Input pins Voltage on output pins Storage Temperature Operative ambient temp Parameter Value -0.3 to 4 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -40 to +150 -20 to +85 Unit V V V C C
THERMAL DATA
Symbol Rth j-amb Parameter Thermal resistance Junction to Ambient Value 85 Unit C/W
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PIN DESCRIPTION
SO28 TQFP44 LFBGA64 1 29 B5 2 30 B4 3 31 A4 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 32 34 36 38 40 42 44 2 3 5 6 7 8 10 11 12 13 15 19 21 22 24 25 26 27 20 18 16 14 37 39 41 43 35 4 28 33 B3 A1 B2 D4 D1 E2 F2 H1 H3 F3 E4 G4 G5 F5 G6 G7 G8 F7 E7 C8 D7 A7 B6 A5 C5 C7 E6 F6 F8 C3 E3 D2 F1 C2 G3 C6 A2 Pin Name VDD_1 VSS_1 SDA SCL SDI SCKR BIT_EN SRC_INT/SCK_ADC SDO SCKT LRCLKT OCLK VSS_2 VDD_2 VSS_3 VDD_3 PVDD PVSS FILT XTO XTI VSS_4 VDD_4 TESTEN SDI_ADC RESET LRCK_ADC OUT_CLK/ DATA_REQ IODATA[0] IODATA[1] IODATA[2] IODATA[3] IODATA[4] IODATA[5] IODATA[6] IODATA[7] GPIO_STROBE GPSO_REQ GPSO_SCKR GPSO_DATA Type Function Supply Voltage Ground i2C Serial Data + Acknowledge 2 I C Serial Clock Receiver Serial Data Receiver Serial Clock Bit Enable Interrupt Line/ADC Serial Clock TransmitterSerial Data(PCM Data) Transmitter Serial Clock Transmitter Left/Right Clock Oversampling Clock for DAC Ground Supply Voltage Ground Supply Voltage PLL Power PLL Ground PLL Filter Ext. Capacitor Conn. Crystal Output Crystal Input (Clock Input) Ground Supply Voltage Test Enable ADC Data Input System Reset ADC Left/Right Clock Buffered Output Clock/ Data Request Signal GPIO Data Line GPIO Data Line GPIO Data Line GPIO Data Line GPIO Data Line GPIO Data Line GPIO Data Line GPIO Data Line GPIO Strobe Signal GPSO Request Signal GPSO Serial Clock GPSO Serial Data PAD Description
I/O I I I I I O O O I/O
CMOS Input Pad Buffer CMOS 4mA Output Drive CMOS Input Pad Buffer CMOS Input Pad Buffer CMOS Input Pad Buffer CMOS Input Pad Buffer with pull up CMOS Input Pad Buffer CMOS CMOS CMOS CMOS CMOS 4mA Output Drive 4mA Output Drive 4mA Output Drive Input Pad Buffer 4mA Output Drive
O O I
CMOS 4mA Output Drive Specific Level Input Pad (see paragraph 2.1)
I I I I O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I O
CMOS Input Pad Buffer with pull up CMOS Input Pad Buffer CMOS Input Pad Buffer with pull up CMOS Output Pad Buffer CMOS 4mA Output Drive CMOS 4mA Schmitt Trigger Bidir Pad Buffer
CMOS Output Pad Buffer CMOS Input Pad Buffer CMOS Output Pad Buffer
Note: In functional mode TESTEN must be connected to VDD.
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STA015-STA015B-STA015T
1. ELECTRICAL CHARACTERISTICS: VDD = 3.3V 0.3V; Tamb = 0 to 70C; Rg = 50 unless otherwise specified DC OPERATING CONDITIONS
Symbol VDD Tj Power Supply Voltage Operating Junction Temperature Parameter Value 2.4 to 3.6V -20 to 125C
GENERAL INTERFACE ELECTRICAL CHARACTERISTICS
Symbol IIL IIH Vesd Parameter Low Level Input Current Without pull-up device High Level Input Current Without pull-up device Electrostatic Protection Test Condition Vi = 0V Vi = VDD Leakage < 1A Min. -10 -10 2000 Typ. Max. 10 10 Unit A A V Note 1 1 2
Note 1: The leakage currents are generally very small, < 1nA. The value given here is a maximum that can occur after an electrostatic stress on the pin. Note 2: Human Body Model.
DC ELECTRICAL CHARACTERISTICS
Symbol VIL VIH Vol Voh Parameter Low Level Input Voltage High Level Input Voltage Low Level Output Voltage High Level Output Voltage Iol = Xma 0.85*VDD 0.8*VDD 0.4V Test Condition Min. Typ. Max. 0.2*VDD Unit V V V V 1, 2 1, 2 Note
Note 1: Takes into account 200mV voltage drop in both supply lines. Note 2: X is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability.
Symbol Ipu Rpu
Parameter Pull-up current Equivalent Pull-up Resistance
Test Condition Vi = 0V; pin numbers 7, 24 and 26
Min. -25
Typ. -66 50
Max. -125
Unit A k
Note 1
Note 1: Min. condition: VDD = 2.7V, 125C Min process Max. condition: V DD = 3.6V, -20C Max.
POWER DISSIPATION
Symbol PD Parameter Power Dissipation @ VDD = 3V Test Condition Sampling_freq 24 kHz Sampling_freq 32 kHz Sampling_freq 48 kHz Min. Typ. 76 79 85 Max. Unit mW mW mW Note
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STA015-STA015B-STA015T
Figure 3. Test Circuit (refer to SO28 package)
3 4 9 10 11 12 5 13 16 6 7 25 8 27 21 20 22 17 4.7F 100nF 18 26 RESET 24 TESTEN 470pF VSS PVSS PVDD PVSS
D00AU1143
SDA SCL SDO SCKT LRCKT OCLK SDI SCKR BIT_EN SDI_ADC SCR_INT LRCK_ADC XTI XTO 10K
OUT_CLK/DATA_REQ VDD 100nF VSS VDD 100nF VSS VDD 100nF VSS VDD 100nF VDD 4.7F PVDD VSS
28 1
2 14
15 23
19
1K 4.7nF
PVSS
Figure 4. Test Load Circuit
VDD IOL
Test Load
Output SDA Other Outputs IOL 1mA 100A 100A IOH CL 100pF 100pF VREF 3.6V 1.5V
OUTPUT
VREF CL IOH
D98AU967
2. FUNCTIONAL DESCRIPTION 2.1 - Clock Signal The STA015 input clock is derivated from an external source or from a industry standard crystal oscillator, generating input frequencies of 10, 14.31818 or 14.7456 MHz.
Symbol VIL VIH Parameter Low Level Input Voltage High Level Input Voltage
Other frequencies may be supported upon request to STMicroelectronics. Each frequency is supported by downloading a specific configuration file, provided by STM XTI is an input Pad with specific levels.
Test Condition
Min. VDD-0.8
Typ.
Max. VDD-1.8
Unit V V
CMOS compatibility The XTI pad low and high levels are CMOS compatible; XTI pad noise margin is better than typical CMOS pads. TTL compatibility The XTI pad low level is compatible with TTL while the high level is not compatible (for example if VDD = 3V TTL min high level = 2.0V while XTI min high level = 2.2V)
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STA015-STA015B-STA015T
Figure 5. PLL and Clocks Generation System
XTI
N
PFD
CP
C
R C
M
VCO
Disable PLL
FRAC
Switching Circuit
XTI2OCLK
OCLK
X
DCLK
Update FRAC
S
XTI2DSPCLK
2.4 - PCM Output Interface The decoded audio data are output in serial PCM format. The interface consists of the following signals: SDO PCM Serial Data Output SCKT PCM Serial Clock Output LRCLK Left/Right Channel Selection Clock The output samples precision is selectable from Figure 6. PCM Output Formats
16 SCLK Cycles LRCKT 16 SCLK Cycles
16 to 24 bits/word, by setting the output precision with PCMCONF (16, 18, 20 and 24 bits mode) register. Data can be output either with the most significant bit first (MS) or least significant bit first (LS), selected by writing into a flag of the PCMCONF register. Figure 8 gives a description of the several STA015 PCM Output Formats. The sample rates set decoded by STA015 is described in Table 1.
16 SCLK Cycles 16 SCLK Cycles
M S
16 SCLK Cycles
SDO
M S
L S
M S
L S
M S
L S
L S
PCM_ORD = 0 PCM_PREC is 16 bit mode PCM_ORD = 1 PCM_PREC is 16 bit mode
SDO
L S
M S
L S
M S
L S
M S
L S
M S
32 SCLK Cycles LRCKT 32 SCLK Cycles
32 SCLK Cycles 32 SCLK Cycles
M S
32 SCLK Cycles
SDO
M S
L S
0
L S
M S
L S
0
L S
M S
L S
0
L S
L S
0
PCM_FORMAT = 1 PCM_DIFF = 1
L S
SDO
0
M S
0
M S
0
M S
M S
0
M S
M S
PCM_FORMAT = 0 PCM_DIFF = 0 PCM_FORMAT = 0 PCM_DIFF = 1
SDO
0
M S
L S
0
L S
0M S
L S
0
L S
0
L S
0
L S
0
L S
0
L S
SDO
MSB
M S
MSB
M S
MSB
M S
MSB
M S
PCM_FORMAT = 1 PCM_DIFF = 1
Table 1: MPEG Sampling Rates (KHz)
MPEG 1 48 44.1 32 8/44 MPEG 2 24 22.05 16 MPEG 2.5 12 11.025 8
STA015-STA015B-STA015T
normally to operate in Broadcast Mode. In both modes the MPEG Synchronisation is automatic and transparent to the user. 2.6 - STA015 Decoding States There are three different decoder states: Idle, Init, and Decode. Commands to change the de2 coding states are described in the STA015 I C registers description. Idle Mode In this mode the decoder is waiting for the RUN command. This mode should be used to initialise the configuration registers of the device. The DAC connected to STA015 can be initialised during this mode (set MUTE to 1).
PLAY X X MUTE 0 1 Clock State Not Running Running PCM Output 0 0
2.5 - STA015 Operation Mode The STA015 can work in two different modes, called Multimedia Mode and Broadcast Mode. In Multimedia Mode (default mode) STA015 decodes the incoming bitstream, acting as a master of the data communication from the source to itself. This control is done by a specific buffer management, controlled by STA015 embedded software. The data source, by monitoring the DATA_REQ line, send to STA015 the input data, when the signal is high (default configuration). The communication is stopped when the DATA_REQ line is low. In this mode the fractional part of the PLL is disabled and the audio clocks are generated at nominal rates. Fig. 7 describes the default DATA_REQ signal behaviour. Programming STA015 it is possible to invert the polarity of the DATA_REQ line (register REQ_POL).
Figure 7.
SOURCE STOPS TRANSMITTING DATA DATA_REQ
SOURCE STOPS TRANSMITTING DATA
Init Mode "PLAY" and "MUTE" changes are ignored in this mode. The internal state of the decoder will be updated only when the decoder changes from the state "init" to the state "decode". The "init" phase ends when the first decoded samples are at the output stage of the device. Decode Mode This mode is completely described by the following table:
SOURCE SEND DATA TO STA015
D00AU1144
In Broadcast Mode, STA015 works receiving a bitstream with the input speed regulated by the source. In this configuration the source has to guarantee that the bitrate is equivalent to the nominal bitrate of the decoded stream. To compensate the difference between the nominal and the real sampling rates, the STA015 embedded software controls the fractional PLL operation. Portable or Mobile applications need
PLAY 0 0 1 1
MUTE 0 1 0 1
Clock State Not Running Running Running Running
PCM Output 0 0 Decoded Samples 0
Decoding No No Yes Yes
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Figure 8. MPEG Decoder Interfaces.
P
XTI XTO FILT IIC
SCL
SDA
DATA_REQ SDI DATA SOURCE SCKR BIT_EN
PLL
IIC SDO
MPEG DECODER
SERIAL AUDIO INTERFACE RX TX
SCKT LRCKT
DAC
OCLK
D98AU912
Figure 9. Serial Input Interface Clocks
SDI DATA IGNORED
SCKR
SCLK_POL=0
SCKR
SCLK_POL=4
BIT_EN
DATA VALID
D98AU968A
DATA IGNORED
2.2 - Serial Input Interface STA015 receives the input data (MSB first) thought the Serial Input Interface (Fig.5). It is a serial communication interface connected to the SDI (Serial Data Input) and SCKR (Receiver Serial Clock). The interface can be configured to receive data sampled on both rising and falling edge of the SCKR clock. The BIT_EN pin, when set to low, forces the bitstream input interface to ignore the incoming data. For proper operation Bit_EN line should be toggled only when SCRK is stable low (for both SCLK_POL configuration) The possible configurations are described in Fig. 9. 2.3 - PLL & Clock Generator System When STA015 receives the input clock, as described in Section 2.1, and a valid layer III input bitstream, the internal PLL locks, providing to the DSP Core the master clock (DCLK), and to the
Audio Output Interface the nominal frequencies of the incoming compressed bit stream. The STA015 PLL block diagram is describedin Figure 5. The audio sample rates are obtained dividing the oversampling clock (OCLK) by software programmable factors. The operation is done by STA015 embeddedsoftware and it is transparentto the user. The STA015 PLL can drive directly most of the commercial DACs families, providing an over sampling clock, OCLK, obtained dividing the VCO frequency with a software programmable dividers. 2.4 - GPSO Output Interface In order to retrieve ADPCM encoded data a General Purpose Serial Output interface is available (in TQFP44 and LFBGA64 packages only). The maximum frequency for clock is the GPSO_SCKR DSP system clock frequency divided by 3 (i.e. 8.192 MHz @ 24.58MHz). The interface is based on a simple and configurable 3lines protocol, as described by figure 10.
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STA015-STA015B-STA015T
Figure 10.
GPSO_SCKR
STA015
GPSO_DATA GPSO_REQ
MCU
GPSO_SCKR
GPSO_REQ
GPSO_DATA
D00AU1145
To enable the GPSO interface bit GEN of GPSO_ENABLE register must be set. Using the GPSO_CONF register the protocol can be configured in order to provide outcoming data on rising/falling edge of GPSO_SCKR input clock; the GPSO_REQ request signal polarity (usually connected to an MCU interrupt line) can be configured as well. ADC Inteface Beside the serial input interface based on SDI and SCKR lines a 3 wire flexible and user configurable input interface is also available, suitable to interface with most A/D converters. To configure 2 this interface 4 specific I C registers are available (ADC_ENABLE, ADC_CONF, ADC_WLEN and ADC_WPOS). Refer to registers description for more details. General Purpose I/O Interface A new general purpose I/O interface has been added to this device (TQFP44 and LFBGA64 only). Actually only the strobe line is used in
INPUT (data to encode) ADC I/F (SDI_ADC + LRCK_ADC + SCK_ADC) ADC I/F (SDI_ADC + LRCK_ADC + SCK_ADC) SERIAL I/F (SCKR + SDI + DATA_REQ) SERIAL I/F (SCKR + SDI + DATA_REQ) (*)
(*) STA013 Compatible mode
ADPCM to provide an interrupt; the use of the other bits is still to be defined. The related configuration register is GPIO_CONF. See the following summary for related pin usage:
Name I/ODATA [0] .................... I/ODATA [7] GPIO_STROBE Description GPIO data line Dir I/O .... I/O I/O
GPIO strobe line
2.5 ADPCM Encoding: Overview According to the previously described interfaces there are 4 ways to manage ADPCM data stream while encoding. Input interface can be either the serial receiver block (SDI + SCKR + DATA_REQ lines) or the ADC specific interface. Output interfaces can be either the I 2C bus (with or without interrupt line) or the GPSO high-speed serial interface (GPSO_REQ + GPSO_ DATA + GPSO_SCKR lines). This result in the following 4 methods to handle encoding flow:
Output (encoded data) Available on package TQFP44 LFBGA64 SO28/TQFP44 LFBGA64 TQFP44 LFBGA64 SO28/TQFP44 LFBGA64
GPSO I/F (GPSO_REQ + GPSO_DATA + GPSO_SCKR) 2 I C + Interrupt (SCL + SDA + DATA_REQ) GPSO I/F (GPSO_REQ + GPSO_DATA + GPSO_SCKR) I2C (polling) (SCL + SDA)
Figure. 11
LRCK_ADC SDI_ADC SCK_ADC ADC I/F MUX ENCOD ENGINE SERIAL RECEIVER I2C SDA SCL DATA_REQ
D99AU1064
GPSO_REQ GPSO GPSO_DATA GPSO_SCKR
SDI SCKR DATA_REQ
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STA015-STA015B-STA015T
The following 4 figures (fig. 12, 13, 14, 15) show the available connection diagrams as for as ADPCM encoding function. As shown in the figures some configuration is not available in SO28 package.
Figure 12. Input from BITSTREAM, Output from I2C
SDI SCKR DATA_REQ BIT_EN I 2C
LRCKT SCKT
MCU
STA015
SO28 TQFP44 LFBGA64
SDO OCLK
DAC
D99AU1121A
Figure 14. Input from BITSTREAM, Output from GPSO Figure 13. Input from ADC, Output from I2C + IRQ
I2 C DATA_REQ LRCKT SCKT
MCU GPSO_DATA GPSO_SCKR GPSO_REQ SDI SCKR DATA_REQ BIT_EN
LRCKT SCKT
STA015
TQFP44 LFBGA64
SDO OCLK
DAC
MCU SDO SDI_ADC ADC SLAVE
I2C
D99AU1122A
STA015
SO28 TQFP44 LFBGA64
DAC
Figure 15. Input from ADC, Output from GPSO
OCLK
GPSO_DATA MCU
MCU I2 C DATA_REQ LRCKT
GPSO_SCKR GPSO_REQ
LRCKT SCKT
STA015
LRCK_ADC SCK_ADC ADC MASTER SDI_ADC SO28 TQFP44 LFBGA64
SCKT DAC SDO OCLK
LRCK_ADC SCK_ADC ADC MASTER
D99AU1123A
STA015
TQFP44 LFBGA64
DAC SDO OCLK
D99AU1124A
SDI_ADC
3 - I2C BUS SPECIFICATION The STA015 supports the I2C protocol. This protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the others as the slave. The master always starts the transfer and provides the serial clock for synchronisation. The STA015 is always a slave device in all its communications.
3. 1 - COMMUNICATION PROTOCOL 3.1.0 - Data transition or change Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock is high are used to identify START or STOP condition. 3.1.1 - Start condition START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A START condition must precede any command for data transfer.
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3.1.2 - Stop condition STOP is identified by low to high transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A STOP condition terminates communications between STA015 and the bus master. 3.1.3 - Acknowledge bit An acknowledge bit is used to indicate a successful data transfer. The bus transmitter, either master or slave, releases the SDA bus after sending 8 bit of data. During the 9th clock pulse the receiver pulls the SDA bus low to acknowledge the receipt of 8 bits of data. 3.1.4 - Data input During the data input the STA015 samples the SDA signal on the rising edge of the clock SCL. For correct device operation the SDA signal has to be stable during the rising edge of the clock and the data can change only when the SCL line is low. 3.2 - DEVICE ADDRESSING To start communication between the master and the STA015, the master must initiate with a start condition. Following this, the master sends onto the SDA line 8 bits (MSB first) corresponding to the device select address and read or write mode. Figure 16. Write Mode Sequence
ACK BYTE WRITE START DEV-ADDR SUB-ADDR ACK
The 7 most significant bits are the device address 2 identifier, corresponding to the I C bus definition. For the STA015 these are fixed as 1000011. The 8th bit (LSB) is the read or write operation RW, this bit is set to 1 in read mode and 0 for write mode. After a START condition the STA015 identifies on the bus the device address and, if a match is found, it acknowledges the identification on SDA bus during the 9th bit time. The following byte after the device identification byte is the internal space address. 3.3 - WRITE OPERATION (see fig. 16) Following a START condition the master sends a device select code with the RW bit set to 0. The STA015 acknowledges this and waits for the byte of internal address. After receiving the internal bytes address the STA015 again responds with an acknowledge. 3.3.1 - Byte write In the byte write mode the master sends one data byte, this is acknowledged by STA015. The master then terminates the transfer by generating a STOP condition. 3.3.2 - Multibyte write The multibyte write mode can start from any internal address. The transfer is terminated by the master generating a STOP condition.
ACK DATA IN
RW
STOP
ACK MULTIBYTE WRITE START DEV-ADDR SUB-ADDR
ACK DATA IN
ACK DATA IN
ACK
RW
D98AU825B
STOP
Figure 17. Read Mode Sequence
ACK CURRENT ADDRESS READ START RANDOM ADDRESS READ START SEQUENTIAL CURRENT READ START ACK SEQUENTIAL RANDOM READ START DEV-ADDR RW SUB-ADDR START ACK DEV-ADDR RW ACK DATA ACK DATA DEV-ADDR DATA NO ACK
RW ACK DEV-ADDR RW RW= ACK HIGH DEV-ADDR DATA SUB-ADDR ACK
STOP ACK DEV-ADDR START ACK DATA RW ACK DATA STOP ACK DATA NO ACK NO ACK DATA STOP NO ACK
D98AU826A
STOP
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3.4 - READ OPERATION (see Fig. 17) 3.4.1 - Current byte address read The STA015 has an internal byte address counter. Each time a byte is written or read, this counter is incremented. For the current byte address read mode, following a START condition the master sends the device address with the RW bit set to 1. The STA015 acknowledges this and outputs the byte addressed by the internal byte address counter. The master does not acknowledge the received byte, but terminates the transfer with a STOP condition. 3.4.2 - Sequential address read This mode can be initiated with either a current address read or a random address read. However in this case the master does acknowledge the data byte output and the STA015 continues to output the next byte in sequence. To terminate the streams of bytes the master does not acknowledge the last received byte, but I2C REGISTERS
HEX_COD $00 $01 $05 $06 $07 $0C $0D $0F $10 $13 $14 $16 $18 $40 - $51 $40 $41 $42 $43 $44 $45 $46 $47 $48 DEC_COD 0 1 5 6 7 12 13 15 16 19 20 22 24 64 - 81 64 65 66 67 68 69 70 71 72 VERSION IDENT PLLCTL [7:0] PLLCTL [20:16] (MF[4:0]=M)
terminates the transfer with a STOP condition. The output data stream is from consecutive byte addresses, with the internal byte address counter automatically incremented after one byte output. 4 - I C REGISTERS The following table gives a description of the MPEG Source Decoder (STA015) register list. The first column (HEX_COD) is the hexadecimal code for the sub-address. The second column (DEC_COD) is the decimal code. The third column (DESCRIPTION) is the description of the information contained in the register. The fourth column (RESET) inidicate the reset value if any. When no reset value is specifyed, the default is "undefined". The fifth column (R/W) is the flag to distinguish register "read only" and "read and write", and the useful size of the register itself. Each register is 8 bit wide. The master shall operate reading or writing on 8 bits only.
2
DESCRIPTION
RESET 0xAC 0xA1 0x0C 0x00 0x01 0x04 0x00 0x00 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xFF 0x00
R/W R (8) R (8) R/W (8) R/W (8) R/W (8) R/W (8) R/W (8) R (8) W (8) R/W(8) R/W(8) R/W(8) R/W(8) R/W (8) R (8) R (8) R (8) R(8) R(8) R(8) R/W (8) R/W (8) R/W (8)
PLLCTL [15:12] (IDF[3:0]=N) REQ_POL SCLK_POL ERROR_CODE SOFT_RESET PLAY MUTE CMD_INTERRUPT DATA_REQ_ENABLE ADPCM_DATA_1 to ADPCM_DATA_18 SYNCSTATUS ANCCOUNT_L ANCCOUNT_H HEAD_H[23:16] HEAD_M[15:8] HEAD_L[7:0] DLA DLB DRA
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I2C REGISTERS (continued)
HEX_COD $49 $4D $4E $50 $51 $52 $52 $53 $54 $55 $56 $61 $63 $64 $65 $67 $68 $69 $6A $71 $72 $77 $78 $79 $7A $7B $7C $7D $7E - B5 $B6 $B8 $B9 $BA $BB $BC $BD $BE $BF $C0 $C1 $C2
Note: 1) The HEX_COD is the hexadecimal adress that the microcontroller has to generate to access the information. 2) RESERVED: register used for production test only, or for future use.
DEC_COD 73 77 78 80 81 82 82 83 84 85 86 97 99 100 101 103 104 105 106 113 114 119 120 121 122 123 124 125 126 - 181 182 184 185 186 187 188 189 190 191 192 193 194 DRB CHIP_MODE CRCR MFSDF_441 PLLFRAC_441_L
DESCRIPTION
RESET 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x03 0x21 0x00 0x07 0x00 0x46 0x5B 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x0F 0x00 0x00
R/W R/W (8) R/W (2) R/W (1) R/W (8) R/W (8) R/W (1) R/W (8) R/W (4) R/W (8) R/W (8) R/W (8) R/W (8) R/W (8) R/W (8) R/W (8) R (8) R (8) R (8) R (8) R (8) R/W (8) R/W (8) R/W (8) R/W (8) R/W (8) R/W (8) R/W (8) R/W (8) R (8) R/W (1) R/W (2) R/W (1) R/W (2) R/W (1) R/W (5) R/W (8) R/W (8) R/W (2) R/W (5) R/W (5) R/W (8)
ADPCM_DATA_READY PLLFRAC_441_H ADPCM_SAMPLE_FREQ PCM DIVIDER PCMCONF PCMCROSS MFSDF (X) DAC_CLK_MODE PLLFRAC_L PLLFRAC_H FRAME_CNT_L FRAME_CNT_M FRAME_CNT_H AVERAGE_BITRATE SOFTVERSION RUN TREBLE_FREQUENCY_LOW TREBLE_FREQUENCY_HIGH BASS_FREQUENCY_LOW BASS_FREQUENCY_HIGH TREBLE_ENHANCE BASS_ENHANCE TONE_ATTEN ANC_DATA_1 to ANC_DATA_56 ISR ADPCM_CONFIG GPSO_ENABLE GPSO_CONF ADC_ENABLE ADC_CONF ADPCM_FRAME_SIZE ADPCM_INT_CFG GPIO_CONF ADC_ WLEN ADC_ WPOS ADPCM_SKIP_FRAME
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4.1 - STA015 REGISTERS DESCRIPTION The STA015 device includes 256 I2C registers. In this document, only the user-oriented registers are described. The undocumented registers are reserved. These registers must never be accessed (in Read or in Write mode). The ReadOnly registers must never be written. The following table describes the meaning of the abbreviations used in the I2C registers description:
Symbol NA UND NC RO WO R/W R/WS Comment Not Applicable Undefined No Charge Read Only Write Only Read and Write Read, Write in specific mode
PLLCTL Address: 0x05 (05) Type: R/W Software Reset: 0xA1 Hardware Reset: 0xA1
MSB b7 b6 b5 b4 b3 b2 b1 LSB b0
XTO_ XTOD OCLK SYS2O PPLD XTI2DS XTI2O UPD_F BUF IS EN CLK IS PCLK CLK RAC
VERSION Address: 0x00 (00) Type: RO
MSB b7 V8 b6 V7 b5 V6 b4 V5 b3 V4 b2 V3 b1 V2 LSB b0 V1
The VERSION register is read-only and it is used to identify the IC on the application board. IDENT Address: 0x01 (01) Type: RO Software Reset: 0xAC Hardware Reset: 0xAC
MSB b7 1 b6 0 b5 1 b4 0 b3 1 b2 1 b1 0 LSB b0 0
UPD_FRAC: when is set to 1, update FRAC in the switching circuit. It is set to 1 after autoboot. XTI2OCLK: when is set to 1, use the XTI as input of the divider X instead of VCO output. It is set to 0 on HW reset. XTI2DSPCLK: when is to 1, set use the XTI as input of the divider S instead of VCO output. It is set to 0 on HW reset. PLLDIS: when set to 1, the VCO output is disabled. It is set to 0 on HW reset. SYS2OCLK: when is set to 1, the OCLK frequency is equal to the system frequency. It is useful for testing. It is set to 0 on HW reset. OCLKEN: when is set to 1, the OCLK pad is enable as output pad. It is set to 1 on HW reset. XTODIS: when is set to 1, the XTO pad is disable. It is set to 0 on HW reset. XTO_BUF: when this bit is set, the pin nr. 28 (OUT_CLOCK/DATA_REQ) is enabled. It is set to 0 after autoboot. PLLCTL (M) Address: 0x06 (06) Type: R/W Software Reset: 0x0C Hardware Reset: 0x0C PLLCTL (N) Address: 0x07 (07) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 The M and N registers are used to configure the STA015 PLL by DSP embedded software. M and N registers are R/W type but they are completely controlled, on STA015, by DSP software.
IDENT is a read-only register and is used to identify the IC on an application board. IDENT always has the value "0xAC"
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REQ_POL Address: 0x0C (12) Type: R/W Software Reset: 0x01 Hardware Reset: 0x00 The REQ_POL registers is used to program the polarity of the DATA_REQ line.
MSB b7 0 b6 0 b5 0 b4 0 b3 0 b2 0 b1 0 LSB b0 1 MSB b7 X b6 X b5 EC5 b4 EC4 b3 EC3 b2 EC2 b1 EC1 LSB b0 EC0
X = don't care ERROR_CODE register contains the last error occourred if any. The codes can be as follows:
Code 0x00 0x01 0x02 0x04 0x10 0x2X 0x3X Description No error since the last SW or HW Reset CRC Failure DATA not available Ancillary data not read Audio synch word not found MPEG Header error MPEG Decoding errors
Default polarity (the source sends data when the DATA_REQ line is high)
MSB b7 0 b6 0 b5 0 b4 0 b3 0 b2 1 b1 0 LSB b0 1
Inverted polarity (the source sends data when the DATA_REQ line is low) SCKL_POL Address: 0x0D (13) Type: R/W Software Reset: 0x04 Hardware Reset: 0x04
MSB b7 X b6 X b5 X b4 X b3 X b2 0 1 b1 0 0 LSB b0 0 0 (1) (2)
SOFT_RESET Address: 0x10 (16) Type: WO Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 X b6 X b5 X b4 X b3 X b2 X b1 X LSB b0 0 1
X = don't care; 0 = normal operation; 1 = reset When this register is written, a soft reset occours. The STA015 core command register and the interrupt register are cleared. The decoder goes in to idle mode. PLAY Address: 0x13 (19) Type: R/W Software Reset: 0x01 Hardware Reset: 0x01
MSB b7 X b6 X b5 X b4 X b3 X b2 X b1 X LSB b0 0 1
X = don't care SCKL_POL is used to select the working polarity of the Input Serial Clock (SCKR). (1) If SCKL_POL is set to 0x00, the data (SDI) are sent with the falling edge of SCKR and sampled on the rising edge. (2) If SCKL_POL is set to 0x04, the data (SDI) are sent with the rising edge of SCKR and sampled on the falling edge. ERROR_CODE Address: 0x0F (15) Type: RO Software Reset: 0x00 Hardware Reset: 0x00
X = don't care; 0 = normal operation; 1 = play The PLAY command is handled according to the state of the decoder, as described in section 2.5. PLAY only becomes active when the decoder is in DECODE mode.
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MUTE Address: 0x14 (20) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 X b6 X b5 X b4 X b3 X b2 X b1 X LSB b0 0 1
CMD_INTERRUPT Address: 0x16 (22) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 X b6 X b5 X b4 X b3 X b2 X b1 X LSB b0 0 1
X = don't care; 0 = normal operation; 1 = mute The MUTE command is handled according to the state of the decoder, as described in section 2.5. MUTE sets the clock running.
X = don't care; 0 = normal operation; 1 = write into I 2C/Ancillary Data The INTERRUPT is used to give STA015 the command to write into the I2C/Ancillary Data Buffer (Registers: 0x7E ... 0xB5). Every time the Master has to extract the new buffer content it writes into this register, setting it to a non-zero value.
DATA_REQ_ENABLE Address: 0x18 (24) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 X X b6 X X b5 X X b4 X X b3 X X b2 0 1 b1 X X LSB b0 X X Description buffered output clock request signal
The DATA_REQ_ENABLE register is used to configure Pin n. 28 working as buffered output clock or data request signal, used for multimedia SYNCSTATUS Address: 0x40 (64) Type: RO Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 X b6 X b5 X b4 X b3 X b2 X
mode. The buffered Output Clock has the same frequency than the input clock (XTI)
LSB b1 SS1 0 0 1 b0 SS0 0 1 0 Research of sync word Wait for Confirmation Synchronised Description
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ADPCM_DATA BUFFER Address: 0x40 - 0x51 (64 - 81) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 b6 b5 b4 b3 b2 b1 ENCODED DATA N to N+18 LSB b0
HEAD_L[7:0]
MSB b7 H7 b6 H6 b5 H5 b4 H4 b3 H3 b2 H2 b1 H1 LSB b0 H0
ANCCOUNT_L Address: 0x41 (65) Type: RO Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 AC7 b6 AC6 b5 AC5 b4 AC4 b3 AC3 b2 AC2 b1 AC1 LSB b0 AC0
ANCCOUNT_H Address: 0x42 (66) Type: RO Software Reset: 0x00 Hardware Reset: 0x00 ANCCOUNT_H
MSB b7 b6 b5 b4 b3 b2 b1 AC15 AC14 AC13 AC12 AC11 AC10 AC9 LSB b0 AC8
Address: 0x43, 0x44, 0x45 (67, 68, 69) Type: RO Software Reset: 0x00 Hardware Reset: 0x00 Head[1:0] emphasis Head[2] original/copy Head[3] copyrightHead [5:4] mode extension Head[7:6] mode Head[8] private bit Head[9] padding bit Head[11:10] sampling frequency index Head[15:12] bitrate index Head[16] protection bit Head[18:17] layer Head[19] ID Head[20] ID_ex The HEAD registers can be viewed as logically concatenated to store the MPEG Layer III Header content. The set of three registers is updated every time the synchronisation to the new MPEG frame is achieved The meaning of the flags are shown in the following tables: MPEG IDs
IDex 0 0 ID 0 1 0 1 MPEG 2.5 reserved MPEG 2 MPEG 1
ANCCOUNT registers are logically concatenated and indicate the number of Ancillary Data bits available at every correctly decoded MPEG frame. HEAD_H[23:16]
MSB b7 X b6 X b5 X b4 H20 b3 H19 b2 H18 b1 H17 LSB b0 H16
1 1
x = don't care HEAD_M[15:8]
MSB b7 H15 b6 H14 b5 H13 b4 H12 b3 H1`1 b2 H10 b1 H9 LSB b0 H8
Layer in Layer III these two flags must be set always to "01". Protection_bit It equals "1" if no redundancy has been added and "0" if redundancy has been added.
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Bitrate_index indicates the bitrate (Kbit/sec) depending on the MPEG ID.
bitrate index '0000' '0001' '0010' '0011' '0100' '0101' '0110' '0111' '1000' '1001' '1010' '1011' '1100' '1101' '1110' '1111' ID = 1 free 32 40 48 56 64 80 96 112 128 160 192 224 256 320 forbidden ID = 0 free 8 16 24 32 40 48 56 64 80 96 112 128 144 160 forbidden
Private bit Bit for private use. This bit will not be used in the future by ISO/IEC. Mode Indicates the mode according to the following table. The joint stereo mode is intensity_stereo and/or ms_stereo.
mode '00' '01' '10' '11' mode specified stereo joint stereo (intensity_stereo and/or ms_stereo) dual_channel single_channel (mono)
Mode extension These bits are used in joint stereo mode. They indicates which type of joint stereo coding method is applied. The frequency ranges, over which the intensity_stereo and ms_stereo modes are applied, are implicit in the algorithm. Copyright If this bit is equal to '0', there is no copyright on the bitstream, '1' means copyright protected. Original/Copy This bit equals '0' if the bitstream is a copy, '1' if it is original. Emphasis Indicates the type of de-emphasis that shall be used.
emphasis '00' '01' '10' '11' emphasis specified none 50/15 microseconds reserved CCITT J,17
Sampling Frequency indicates the sampling frequency of the encoded audio signal (KHz) depending on the MPEG ID
Sampling Frequency '00' '01' '10' '11' MPEG1 44.1 48 32 reserved MPEG2 22.05 24 16 reserved MPEG2.5 11.03 12 8 reserved
Padding bit if this bit equals '1', the frame contains an additional slot to adjust the mean bitrate to the sampling frequency, otherwise this bit is set to '0'. DLA Address: 0x46 (70) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 DLA7 0 0 0 : 0 b6 DLA6 0 0 0 : 1 b5 DLA5 0 0 0 : 1 b4 DLA4 0 0 0 : 0 b3 DLA3 0 0 0 : 0 b2 DLA2 0 0 0 : 0
b1 DLA1 0 0 1 : 0
LSB b0 DLA0 0 1 0 : 0
Description OUTPUT ATTENUATION NO ATTENUATION -1dB -2dB : -96dB
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DLA register is used to attenuate the level of audio output at the Left Channel using the butterfly shown in Fig. 18. When the register is set to Figure 18. Volume Control and Output Setup
DLA X DLB X DRB X DRA DSP Right Channel X
255 (0xFF), the maximum attenuation is achieved. A decimal unit correspond to an attenuation step of 1 dB.
DSP Left Channel
+
Output Left Channel
+
Output Right Channel
D97AU667
DLB Address: 0x47 (71) Type: R/W Software Reset: 0xFF Hardware Reset: 0xFF
MSB b7 DLB7 0 0 0 : 0 b6 DLB6 0 0 0 : 1 b5 DLB5 0 0 0 : 1 b4 DLB4 0 0 0 : 0 b3 DLB3 0 0 0 : 0 b2 DLB2 0 0 0 : 0 b1 DLB1 0 0 1 : 0 LSB b0 DLB0 0 1 0 : 0 Description OUTPUT ATTENUATION NO ATTENUATION -1dB -2dB : -96dB
DLB register is used to re-direct the Left Channel on the Right, or to mix both the Channels. DRA Address: 0x48 (72) Type: R/W Software Reset: 0X00 Hardware Reset: 0X00
MSB b7 DRA7 0 0 0 : 0 b6 DRA6 0 0 0 : 1 b5 DRA5 0 0 0 : 1 b4 DRA4 0 0 0 : 0 b3 DRA3 0 0 0 : 0 b2 DRA2 0 0 0 : 0
Default value is 0x00, corresponding at the maximum attenuation in the re-direction channel.
LSB b1 DRA1 0 0 1 : 0 b0 DRA0 0 1 0 : 0 Description OUTPUT ATTENUATION NO ATTENUATION -1dB -2dB : -96dB
DRA register is used to attenuate the level of audio output at the Right Channel using the butterfly shown in Fig. 11. When the register is set to
255 (0xFF), the maximum attenuation is achieved. A decimal unit correspond to an attenuation step of 1 dB.
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DRB Address: 0x49 (73) Type: R/W Software Reset: 0xFF Hardware Reset: 0xFF
MSB b7 DRB7 0 0 0 : 0 b6 DRB6 0 0 0 : 1 b5 DRB5 0 0 0 : 1 b4 DRB4 0 0 0 : 0 b3 DRB3 0 0 0 : 0 b2 DRB2 0 0 0 : 0 b1 DRB1 0 0 1 : 0 LSB b0 DRB0 0 1 0 : 0 Description OUTPUT ATTENUATION NO ATTENUATION -1dB -2dB : -96dB
DRB register is used to re-direct the Right Channel on the Left, or to mix both the Channels. CHIP_MODE Address: 0x4D (77) Type: R/W Hardware Reset: 0x00 Using this register it's possible to select which operation will be performed by the DSP. Possible values are: 0x00 - MP3 decoding 0x01 - Reserved 0x02 - ADPCM Encoder 0x03 - ADPCM Decoder The DSP will check for the value of this register right after the RUN command ha s been issued (refer to RUN register). After that no more checks will be performed: therefore a SOFT_RESET must be generated in order to change the device mode. CRCR Address: 0x4E (78) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 X b6 X b5 X b4 X b3 X b2 X b1 X LSB b0 CRCEN
Default value is 0x00, corresponding at the maximum attenuation in the re-direction channel. curs, the current frame is skipped and the decoder is muted. The ERROR_CODE register is affected with the value 0x01. If CRC_EN bit is set, the result of the CRC check is ignored, but the ERROR_CODE register is nevertheless affected with the value 0x01 if a discrepance has occurred. MFSDF_441 Address: 0x50 (80) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 X b6 X b5 X b4 M4 b3 M3 b2 M2 b1 M1 LSB b0 M0
This register contains the value for the PLL X driver for the 44.1KHz reference frequency. The VCO output frequency, when decoding 44.1KHzbitstream, is divided by (MFSDF_441 +1) PLLFRAC_441_L Address: 0x51 (81) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 PF7 b6 PF6 b5 PF5 b4 PF4 b3 PF3 b2 PF2 b1 PF1 LSB b0 PF0
The CRC register is used to enable/disable the CRC check. If CRC_EN bit is cleared, the CRC value encoded in the bitstream is checked against the hardware one. If a discrepance oc22/44
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ADPCM_DATA_READY Address: 0x52 (82) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 X b6 X b5 X b4 X b3 X b2 X b1 X LSB b0 ADR
Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 X b6 X b5 X b4 b3 b2 b1 ADPCM_SF LSB b0
ADPCM_SF: Adpcm Sample Frequency
0x02 0x0A 0x0E 8KHz 16KHz 32KHz
ADR: Adpcm Data Ready This bit signal (ADPCM encoded data ready) PLLFRAC_441_H Address: 0x52 (82) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 b6 b5 b4 b3 b2 b1 PF9 PF15 PF14 PF13 PF12 PF11 PF10 LSB b0 PF8
PCMDIVIDER Address: 0x54 (84) Type: RW Software Reset: 0x03 Hardware Reset: 0x03
7 PD7 6 PD6 5 PD5 4 PD4 3 PD3 2 PD2 1 PD1 0 PD0
The registers are considered logically concatenated and contain the fractional values for the PLL, for 44.1KHz reference frequency. (see also PLLFRAC_L and PLLFRAC_H registers) ADPCM_SAMPLE_FREQ Address: 0x53 (83) Type: R/W
PCMDIVIDER is used to set the frequency ratio between the OCLK (Oversampling Clock for DACs), and the SCKT (Serial Audio Transmitter Clock). The relation is the following:
SCKT_freq =
OCLK_freq 2 (1 + PCM_DIV)
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The Oversampling Factor (O_FAC) is related to OCLK and SCKT by the following expression: 1) OCLK_freq = O_FAC * LRCKT_ Freq (DAC relation) 2) OCLK_ Freq = 2 * (1+PCM_DIV) * 32* LRCKT_Freq (when 16 bit PCM mode is used) 3) OCLK_ Freq = 2 * (1+PCM_DIV) * 64* LRCKT_Freq (when 32 bit PCM mode is used) 4) PCM_DIV = (O_FAC/64) - 1 in 16 bit mode 5) PCM_DIV = (O_FAC/128) - 1 in 32 bit mode Example for setting:
MSB b7 PD7 0 0 0 0 0 0 b6 PD6 0 0 0 0 0 0 b5 PD5 0 0 0 0 0 0 b4 PD4 0 0 0 0 0 0 b3 PD3 0 0 0 0 0 0 b2 PD2 1 1 0 0 0 0 b1 PD1 1 0 1 1 1 0 LSB b0 PD0 1 1 1 1 0 1 Description 16 16 16 32 32 32 bit mode bit mode bit mode bit mode bit mode bit mode 512 384 256 512 384 256 x Fs x Fs x Fs x Fs x Fs x Fs
for 16 bit PCM Mode O_FAC = 512 ; PCM_DIV = 7 O_FAC = 256 ; PCM_DIV = 3 O_FAC = 384 ; PCM_DIV = 5
for 32 bit PCM Mode O_FAC = 512 ; PCM_DIV = 3 O_FAC = 256 ; PCM_DIV = 1 O_FAC = 384 ; PCM_DIV = 2
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PCMCONF Address: 0x55 (85) Type: R/W Software Reset: 0x21 Hardware Reset: 0x21
MSB b7 X X X X X X X X X X X X X X X b6 ORD 1 0 b5 DIF b4 INV b3 FOR b2 SCL LSB b1 b0 PREC (1) PREC (1) Description PCM order the LS bit is transmitted First PCM order the MS bit is transmitted First The word is right padded The word is left padded LRCKT Polarity compliant to I2S format LRCKT Polarity inverted I2S format Different formats Data are sent on the rising edge of SCKT Data are sent on the falling edge of SCKT 16 bit mode (16 slots transmitted) 18 bit mode (18 slots transmitted) 20 bit mode (20 slots transmitted) 24 bit mode (24 slots transmitted)
0 1 1 0 0 1 1 0 0 0 1 1 0 1 0 1
PCMCONF is used to set the PCM Output Interface configuration: ORD: PCM order. If this bit is set to'1', the LS Bit is transmitted first, otherwise MS Bit is transmiited first. DIF: PCM_DIFF. It is used to select the position of the valid data into the transmitted word. This setting is significant only in 18/20/24 bit/word mode.If it is set to '0' the word is right-padded, otherwise it is left-padded. INV (fig.13): It is used to select the LRCKT clock polarity. If it is set to '1' the polarity is compliant to I2S format (low -> left , high -> right), otherwise the LRCKT is inverted. The default value is '0'. (if I2S have to be selected, must be set to '1' in the STA015 configuration phase). Figure 19. LRCKT Polarity Selection
left left right INV_LRCLK=0
rising edge of SCKT and sampled on the falling. If set to '0' , the data are sent on the falling edge and sampled on the rising. This last option is the most commonly used by the commercial DACs. The default configuration for this flag is '0'. Figure 20. SCKT Polarity Selection
SCKT
SDO
INV_SCLK=0
SCKT
SDO
INV_SCLK=1
LRCKT
right
LRCKT
left
left
INV_LRCLK=1
FOR: FORMAT is used to select the PCM Output Interface format. After hw and sw reset the value is set to 0 corresponding to I2S format. SCL (fig.14): used to select the Transmitter Serial Clock polarity. If set to '1' the data are sent on the
PREC [1:0]: PCM PRECISION It is used to select the PCM samples precision, as follows: '00': 16 bit mode (16 slots transmitted) '01': 18 bit mode (32 slots transmitted) '10': 20 bit mode (32 slots transmitted) '11': 24 bit mode (32 slots transmitted) The PCM samples precision in STA015 can be 16 or 18-20-24 bits. When STA015 operates in 16 (18-20-24) bits mode, the number of bits transmitted during a LRCLT period is 32 (64).
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PCMCROSS Address: 0x56 (86) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 X X X X b6 X X X X b5 X X X X b4 X X X X b3 X X X X b2 X X X X b1 0 0 1 1 LSB b0 0 1 0 1 Description Left channel is mapped on the left output. Right channel is mapped on the Right output Left channel is duplicated on both Output channels. Right channel is duplicated on both Output channels Right and Left channels are toggled
The default configuration for this register is '0x00'. MFSDF (X) Address: 0x61 (97) Type: R/W Software Reset: 0x07 Hardware Reset: 0x07
MSB b7 X b6 X b5 X b4 M4 b3 M3 b2 M2 b1 M1 LSB b0 M0
Fs. When this mode is selected, the default OCLK frequency is 12.288 MHz. PLLFRAC_L ([7:0])
MSB b7 PF7 b6 PF6 b5 PF5 b4 PF4 b3 PF3 b2 PF2 b1 PF1 LSB b0 PF0
The register contains the values for PLL X divider (see Fig. 7). The value is changed by the internal STA015 Core, to set the clocks frequencies, according to the incoming bitstream. This value can be even set by the user to select the PCM interface configuration. The VCO output frequency is divided by (X+1). This register is a reference for 32KHz and 48 KHz input bitstream. DAC_CLK_MODE (99) Address: 0x63 Type: RW Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 X b6 X b5 X b4 X b3 X b2 X b1 X LSB b0 MODE
PLLFRAC_H ([15:8])
MSB b7 b6 b5 b4 b3 b2 b1 PF9 PF15 PF14 PF13 PF12 PF11 PF10 LSB b0 PF8
Address: 0x64 - 0x65 (100 - 101) Type: R/W Software Reset: 0x46 | 0x5B Hardware Reset: 0xNA | 0x5B The registers are considered logically concatenated and contain the fractional values for the PLL, used to select the internal configuration. After Reset, the values are NA, and the operational setting are done when the MPEG synchronisation is achieved. The following formula describes the relationships among all the STA015 fractional PLL parameters:
FRAC 1 MCLK_freq OCLK_Freq = M + 1 + 65536 X + 1 N + 1
This register is used to select the operating mode for OCLK clock signal. If it is set to '1', the OCLK frequency is fixed, and it is mantained to the value fixed by the user even if the sampling frequency of the incoming bitstream changes. It the MODE flag is set to '0', the OCLK frequency changes, and can be set to (512, 384, 256) * Fs. The default configuration for this mode is 256 *
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where: FRAC=256 x FRAC_H + FRAC_L (decimal) These registers are a reference for 48 / 24 / 12 / 32 / 16 / 8KHz audio.
STA015-STA015B-STA015T
FRAME_CNT_L
MSB b7 FC7 b6 FC6 b5 FC5 b4 FC4 b3 FC3 b2 FC2 b1 FC1 LSB b0 FC0
MSB b7 SV7 b6 SV6 b5 SV5 b4 SV4 b3 SV3 b2 SV2 b1 SV1
LSB b0 SV0
After the STA015 boot, this register contains the version code of the embedded software. RUN Address: 0x72 (114) Type: RW Software Reset: 0x00 Hardware Reset: 0x00
MSB LSB b6 X b5 X b4 X b3 X b2 X b1 X b0 RUN b7 X
FRAME_CNT_M
MSB b7 b6 b5 b4 b3 b2 b1 FC9 FC15 FC14 FC13 FC12 FC11 FC10 LSB b0 FC8
FRAME_CNT_H
MSB b7 b6 b5 b4 b3 b2 b1 LSB b0
FC23 FC22 FC21 FC20 FC19 FC18 FC17 FC016
Address: 0x67, 0x68, 0x69 (103 - 104 - 105) Type: RO Software Reset: 0x00 Hardware Reset: 0x00 The three registers are considered logically concatenated and compose the Global Frame Counter as described in the table. It is updated at every decoded MPEG Frame. The registers are reset on both hardware and software reset. AVERAGE_BITRATE Address: 0x6A (106) Type: RO Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 AB7 b6 AB6 b5 AB5 b4 AB4 b3 AB3 b2 AB2 b1 AB1 LSB b0 AB0
Setting this register to 1, STA015 leaves the idle state, starting the decoding process. The Microcontroller is allowed to set the RUN flag, once all the control registers have been initialized. TREBLE_FREQUENCY_LOW Address: 0x77 (119) Type: RW Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 TF7 b6 TF6 b5 TF5 b4 TF4 b3 TF3 b2 TF2 b1 TF1 LSB b0 TF0
TREBLE_FREQUENCY_HIGH Address: 0x78 (120) Type: RW Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 b6 b5 b4 b3 b2 b1 TF9 TF15 TF14 TF13 TF12 TF11 TF10 LSB b0 TF8
AVERAGE_BITRATE is a read-only register and it contains the average bitrate of the incoming bitstream. The value is rounded with an accuracy of 1 Kbit/sec.
SOFTVERSION Address: 0x71 (113) Type: RO
The registers TREBLE_FREQUENCY-HIGH and TREBLE_FREQUENCY-LOW, logically concatenated as a 16 bit wide register, are used to select the frequency, in Hz, where the selected frequency is +12dB respect to the stop band. By setting these registers, the following rule must be kept: Treble_Freq < Fs/2
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STA015-STA015B-STA015T
BASS_FREQUENCY_LOW Address: 0x79 (121) Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 BF7 b6 BF6 b5 BF5 b4 BF4 b3 BF3 b2 BF2 b1 BF1 LSB b0 BF0
Example: Bass = 200Hz Treble = 3kHz TFS
15 14 13 12 11 10 0 0 0 0 1 0 9 1 8 1 7 1 6 0 5 1 4 1 3 1 2 0 1 0 0 0
BASS_FREQUENCY_HIGH Address: 0x7A (122) Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 b6 b5 b4 b3 b2 b1 BF9 BF15 BF14 BF13 BF12 BF11 BF10 LSB b0 BF8
BFS
15 14 13 12 11 10 0 0 0 0 0 0 9 0 8 0 7 1 6 1 5 0 4 0 3 1 2 0 1 0 0 0
TREBLE_ENHANCE Address: 0x7B (123) Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 TE7 b6 TE6 b5 TE5 b4 TE4 b3 TE3 b2 TE2 b1 TE1 LSB b0 TE0
The registers BASS_FREQUENCY_HIGH and BASS_FREQUENCY_LOW, logically concatenated as a 16 bit wide register, are used to select the frequency, in Hz, where the selected frequency is -12dB respect to the pass-band. By setting the BASS_FREQUENCY registers, the following rules must be kept: Bass_Freq <= Treble_Freq Bass_Freq > 0 (suggested range: 20 Hz < Bass_Freq < 750 Hz)
MSB b7 0 0 0 0 b6 0 0 0 0 b5 0 0 0 0 b4 0 0 0 0 b3 1 1 1 1 b2 1 0 0 0 b1 0 1 1 0 LSB b0 0 1 0 1 . . 1 0 1 . . 1 0 0 0
Signed number (2 complement) This register is used to select the enhancement or attenuation STA015 has to perform on Treble Frequency range at the digital signal. A decrement (increment) of a decimal unit corresponds to a step of attenuation (enhancement) of 1.5dB. The allowed Attenuation/Enhan cement range is [-18dB, +18dB].
ENHANCE/ATTENUATION 1.5dB step +18 +16.5 +15 +13.5
0 0 1
0 0 1
0 0 1
0 0 1
0 0 1
0 0 1
0 0 1
+1 0 -1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
0 0 0 0
1 1 1 1
1 1 0 0
-13.5 -15 -16.5 -18
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STA015-STA015B-STA015T
BASS_ENHANCE Address: 0x7C (124) Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 BE7 b6 BE6 b5 BE5 b4 BE4 b3 BE3 b2 BE2 b1 BE1 LSB b0 BE0
This register is used to select the enhancement or attenuation STA015 has to perform on Bass Frequency range at the digital signal. A decrement (increment) of a decimal unit corresponds to a step of attenuation (enhancement) of 1.5dB. The allowed Attenuation/Enhan cement range is [-18dB, +18dB].
Signed number (2 complement)
MSB b7 0 0 0 0 b6 0 0 0 0 b5 0 0 0 0 b4 0 0 0 0 b3 1 1 1 1 b2 1 0 0 0 b1 0 1 1 0 LSB b0 0 1 0 1 . . . 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 . . . 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 0 0 0 -13.5 -15 -16.5 -18 +1 0 -1 ENHANCE/ATTENUATION 1.5dB step +18 +16.5 +15 +13.5
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STA015-STA015B-STA015T
TONE_ATTEN Address: 0x7D (125) Type: RW Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 TA7 b6 TA6 b5 TA5 b4 TA4 b3 TA3 b2 TA2 b1 TA1 LSB b0 TA0
son, before applying Bass & Treble Control, the user has to set the TONE_ATTEN register to the maximum value of enhancement is going to perform. For example, in case of a 0 dB signal (max. level) only attenuation would be possible. If enhancement is desired, the signal has to be attenuated accordingly before in order to reserve a margin in dB. An increment of a decimal unit corresponds to a Tone Attenuationstep of 1.5dB.
In the digital output audio, the full signal is achieved with 0 dB of attenuation. For this reaMSB b7 0 0 0 0 LSB b0 0 1 0 1
. . .
b6 0 0 0 0
b5 0 0 0 0
b4 0 0 0 0
b3 0 0 1 0
b2 0 0 0 0
b1 0 0 1 1
ATTENUATION -1.5dB step 0dB -1.5dB -3dB -4.5dB
0 0 0
0 0 0
0 0 0
0 0 0
1 1 1
0 0 1
1 1 0
0 1 0
-15dB -16.5dB -18dB
5. GENERAL INFORMATION 5.1. MPEG 2.5 Layer III Algorithm.
DEMULTIPLEXING & ERROR CHECK
HUFFMAN DECODING
INVERSE QUANTISATION & DESCALING
IMDCT
INVERSE FILTERBANK
SIDE INFORMATION DECODING ANCILLARY DATA ENCODED AUDIO BITSTREAM (8Kbit/s ... 128Kbit/s)
STEREOPHONIC AUDIO SIGNAL (2*768Kbit/s)
D98AU903
5.2 - MPEG Ancillary Data Description: As specifyed in the ISO standard, the MPEG Layer III frames have a variable bit lenght, and are constant in time depending on the audio samTable2: MPEG Layer III Frames Time Duration
Sampling Frequency (KHz) MPEG Frame Lenght (ms) 48 24 44.1 29 32 36
pling frequencies. The time duration of the Layer III frames is shown in Tab 2.
24 24
22.5 29
16 36
12 48
11.025 48
8 72
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STA015-STA015B-STA015T
ANCILLARY DATA BUFFER Address: 0x7E - 0xB5 (126 - 181) Type: RO Software Reset: 0x00 Hardware Reset: 0x00 STA015 can extract max 56 bytes/MPEG frame. To know the number of A.D. bits available every MPEG frame, the ANCCOUNT_L and ANCCOUNT_H registers (0x41 and 0x42) have to be read. The buffer dimension is 5 bytes, written by STA015 core in sequential order. So the whole set of ancillary data may be accessed in one shot. The timing information to read the buffer can be obtained by reading the FRAME_CNT registers (0x67 - 0x69). ISR Address: 0xB6 (182) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 X b6 X b5 X b4 X b3 X b2 X b1 X LSB b0 0 1
MSB b7 X b6 X b5 X b4 X b3 b2 b1
LSB b0
AA1 AA0 ASM_EN AFM_EN
This register controls ADPCM engine and how data must be compressed.
AFM_EN ADPCM Frame Mode Enable 0= 1= no frames (raw formed) select the framed output formate for ADPCM encoded data Disable stereo mode Enable stereo mode
ASM_EN: ADPCM Stereo Mode Enable 0= 1=
AA0,AA1: ADPCM Algorithm selection The ADPCM encoding/decoding algorithm can be selected according to the following table: AA1 0 0 1 1 AA0 0 1 0 1 DVI algorithm G723-24 algorithm (24kbp/s) G721 algorithm (32kbp/s) G723-40 algorithm (40kbp/s)
X = don't care; 0 = no ancillary data 1 = Ancillary Data Available The ISR is used by the microcontroller to understand when a new ancillary data block is available.
GPSO_ENABLE Address: 0xB9 (185) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 X b6 X b5 X b4 X b3 X b2 X b1 X LSB b0 GEN
ADPCM_CONFIG Address: 0xB8 (184) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
This register enable/disable the GPSO interface. Setting the GEN bit will enable the serial interface for ADPCM data retrieving. Reset GEN bit to disable GPSO interface.
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STA015-STA015B-STA015T
GPSO_CONF Address: 0xBA (186) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 X GSP: b6 X b5 X b4 X b3 X b2 X b1 GRP LSB b0 GSP
ADC_CONF Address: 0xBC (188) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 X b6 X b5 X b4 b3 b2 b1 LSB b0
ALRCS ALRCP ASCP ADC AIIS
GPSO Sclk polarity Using this bit the GPSO_SCLK polarity can be controlled. Clearing GSP bit data on GPSO_DATA line will be provided on the rising edge of GPSO_SCLK (sampling on falling edge). Setting GSP bit data are provided on falling edge of GPSO_SCLK (sampling on rising edge) GPSO Request Polarity This bit is used to determine the polarity of GPSO_REQ signal. If GRP bit is cleared data are valid on GPSO_REQ signal high. If this bit is set data are valid on GPSO_REQ signal low
Using this register the ADC input interface can be configured as follow:
AIIS: ADC I2S mode 0= 1= ADC: sample word must be aligned with LRCK (no I2S mode) sample word not aligned with LRCK (I2S compliant mode) sample word is LSB first sample word is MSB first Data is sampled on rising edge Data is sampled an falling edge
GRP:
ADC Data Config. 0= 1=
ASCP:
ADC Serial Clock Polarity 0= 1=
ADC_ENABLE Address: 0xBB (187) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 X b6 X b5 X b4 X b3 X b2 X b1 X LSB b0 ADCEN
ALRCP: ALRCS:
ADC Left/Right Clock Polarity ADC Left/Right Clock Start value this two bits permit to determine Left/Right clock usage according to the following table: LEFT/RIGHT COUPLE (Data1, Data2) (0, 1) (0, 1) (1, 2) (Data3, Data4) (2, 3) (2, 3) (3, 4)
ALRCP ALRCS 0 1 0 1 0 0 1 1
This register controls if the ADPCM data to be encoded comes from AD interface or from MP3 bitstream input interface. If ADCEN bit is set data to be encoded comes from ADC interface, otherwise data comes from MP3 stream interface
LRCK
DATA
DATA 0
DATA 1
DATA 2
DATA 3
DATA 4
D99AU1065
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STA015-STA015B-STA015T
ADPCM_FRAME_SIZE Address: 0xBD (189) Type: R/W Software Reset: 0x13 Hardware Reset: 0x00
MSB b7 b6 b5 b4 b3 b2 b1 LSB b0
GPIO_CONF Address: 0xBF (191) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 X b6 X b5 X b4 X b3 X b2 X b1 GOSP LSB b0 GISP
AFS7 AFS6 AFS5 AFS4 AFS3 AFS2 AFS1 AFS1
The ADPCM frame size may be adjusted to match a trade-off between the bitrate overhead and the frame length. The frame size (in bytes) is calculated as follow: FRAME size = (ADPCM_FRAME_SIZE * 90) +108 The frame starts with a 5 bytes sync word (0x5354445649) and, after that, a frame header: - 13 bytes for DVI algorithm - 103 bytes for G726 pack algorithms
This register controls how data are strobed on the GPIO interface.
GISP: GPIO Strobe Polarity in INPUT mode 0= 1= GOSP: 0= 1= data strobed an falling edge data strobed on rising edge non inverted inverted
GPIO Strobe Polarity in OUTPUT mode
ADPCM_INT_CFG Address: 0xBE (190) Type: R/W Software Reset: 0x0B Hardware Reset: 0x00
MSB b7 INTL 6 b6 INTL 5 b5 INTL 4 b4 INTL 3 b3 b2 b1 INTL 0 LSB b0 X
ADC_WLEN Address: 0xC0 (192) Type: R/W Software Reset: 0x0F Hardware Reset: 0x0F
MSB b7 X b6 X b5 X b4 b3 b2 b1 LSB b0
AWL4 AWL3 AWL2 AWL1 AWL0
INTL INTL 2 1
To select ADC word length AWL4 through AWL0 bits can be used. This 5 bit value must contain the size of the significant data bits minus one. ADC_WPOS Address: 0xC1 (193) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 X b6 X b5 X b4 b3 b2 b1 LSB b0
Using this register the ADPCM interrupt capability can be properly configured.
INTL0 INTL6 Interrupt Length The interrupt length can be programmed, using this bits, from 0 up to 128 system clock cycles
AWL4 AWL3 AWL2 AWL1 AWL0
These bits specify the position of the sample word referred to the LRCK slot boundary. Bit AWP0 thru AWP4 must be programmed with the number of bits to ignore after the sample word.
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STA015-STA015B-STA015T
The STA015 contains 56 consecutive 8-bit registers corresponding to the maximum number of ancillary data that may be contained in MPEG frame. The ANCCOUNT_L and ANCOUNT_H registers contain the number of ancillary data bits available within the current MPEG frame. To perform ancillary data reading a status register (0xB6 - INTERRUPT_STATUS_REGISTER) is available: bit 0 of this register should be polled by the microcontroller in order to understand when new data are available.
0x7E ------------0xB5
ANC_DATA_1 --------------------------------ANC_DATA_56
0xB6
ISR
5.3. I/O CELL DESCRIPTION (pinout relative to TQFP44 package) 1) CMOS Tristate Output Pad Buffer, 4mA, with Slew Rate Control / Pin numbers 2, 4, 13, 27, 33, 42, 44
EN Z A
D98AU904
OUTPUT PIN Z
MAX LOAD 100pF
2) CMOS Bidir Pad Buffer, 4mA, with Slew Rate Control / Pin numbers 3, 31
EN IO A
INPUT PIN CAPACITANCE
D98AU905
OUTPUT PIN IO
MAX LOAD 100pF
ZI
IO
5pF
3) CMOS Inpud Pad Buffer / Pin numbers 24, 26, 32, 34, 36, 40
A Z
INPUT PIN A
CAPACITANCE 3.5pF
D98AU906
4) CMOS Inpud Pad Buffer with Active Pull-Up / Pin numbers 22, 25, 28, 38
INPUT PIN
A Z
CAPACITANCE 3.5pF
A
D98AU907
5) CMOS Schmitt Trigger Bidir Pad Buffer with active Pull-up, 4mA, with slew rate control / Pin numbers 14, 16, 18, 20, 35, 37, 39, 41, 43
EN IO A
INPUT PIN CAPACITANCE IO 5pF
OUTPUT PIN IO
MAX LOAD 100pF
ZI
D00AU1150
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STA015-STA015B-STA015T
5.4. TIMING DIAGRAMS 5.4.1. Audio DAC Interface a) OCLK in output. The audio PLL is used to clock the DAC
OCLK (OUTPUT)
SDO tsdo SCKT tsckt LRCLK tlrclk
D98AU969
tsdo = 3.5 + pad_timing (Cload_SDO) - pad_timing (Cload_ OCLK) tsckt = 4 + pad_timing (Cload_SCKT) - pad_timing (Cload_ OCLK) tlrckt = 3.5 + pad_timing (Cload_LRCCKT) pad_timing (Cload_ OCLK)
Pad-timing versus load
Load (pF) 25 50 75 100 Pad_timing 2.90ns 3.82ns 4.68ns 5.52ns
Cload_XXX is the load in pF on the XXX output. pad_timing (Cload_XXX) is the propagation delay added to the XXX pad due to the load.
b) OCLK in input.
OCLK (INPUT) thi tlo
SDO tsdo SCKT tsckt LRCLK tlrclk toclk
D98AU970
Thi min = 3ns Tlo min = 3ns Toclk min = 25ns tsdo = 5.5 + pad_timing (Cload_SDO) ns tsckt = 6 + pad_timing (Cload_SCKT) ns tlrckt = 5.5 + pad_timing (Cload_LRCKT) ns
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STA015-STA015B-STA015T
5.4.2. Bitstream input interface (SDI, SCKR, BIT_EN) SCL_POL = 0
BIT_EN t_biten tsckr_min_period SCKR t sckr_min_low t sckr_min_high SCLK_POL=0 t _biten
SDI
IGNORED
VALID
IGNORED
t sdi_setup
tsdi_hold
D98AU971A
5.4.2. Bitstream input interface (SDI, SCKR, BIT_EN) SCL_POL = 1
BIT_EN t_biten tsckr_min_period SCKR t sckr_min_low t sckr_min_high SCLK_POL=4 t _biten
SDI
IGNORED
IGNORED
VALID
IGNORED
tsdi_setup
tsdi_hold
D99AU1038
tsdi_setup_min= 2ns tsdi_hold_min = 3ns tsckr_min_hi = 10ns tsckr_min_low = 10ns tsckr_min_lperiod = 50ns t_biten (min) = 2ns 5.4.3. SRC_INT This is an asynchronous input used in "broadcast' mode. SRC_INT is active low
SRC_INT t_src_hi t_src_low
D98AU972
t_src_low min duration is 50ns (1DSP clock period) t_src_high min duration is 50ns (1DSP clock period) 5.4.4. XTI,XTO and CLK_OUT timings
XTI (INPUT) thi tlo
XTO txto CLK_OUT tclk_out
D98AU973
txto = 1.40 + pad_timing (Cload_XTO) ns tclk_out = 4 + pad_timing (Cload_CLK_OUT) ns
Note: In "multimedia" mode, the CLK_OUT pad is DATA_REQ. In that case, no timing is given between th e XTI input and this pad.
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STA015-STA015B-STA015T
5.4.5. RESET The Reset min duration (t_reset_low_min) is 100ns
RESET
treset_low_min
D98AU974
5.5. CONFIGURATION FLOW
HW RESET
set
PCM-DIVIDER
PCM OUTPUT INTERFACE CONFIGURATION
set
PCM-CONF.
set { PLL PLL PLL PLL
FRAC_441_H, FRAC_441_L, FRAC_H, FRAC_L }
PLL CONFIGURATION FOR: * { 48, 44.1, 32 29, 22.05, 16 12, 11.025, 8 } KHz * MULTIMEDIA MODE see {TAB 5 to TAB12}
set { MFS DF_441, MFSDF }
THE OVERALL SETTING STEPS ARE INCLUDED IN THE STA015 CONFIGURATION FILE AND CAN BE DOWNLOADED IN ONE STEP. STM PROVIDES A SPECIFIC CONFIGURATION FILE FOR EACH SUPPORTED INPUT CLOCK FREQUENCY
set
PLL CTRL
set
SCLK_POL
INPUT SERIAL CLOCK POLARITY CONFIGURATION
set
DATA_REQ_ENABLE
DATA REQUEST PIN ENABLE
set
REQ_POL
DATA REQUEST POLARITY CONFIGURATION
set
RUN
D00AU1146
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STA015-STA015B-STA015T
Table 5: PLL Configuration Sequence For 10MHz Input Clock 256 Oversapling Clock
REGISTER ADDRESS 6 11 97 80 101 82 100 81 5 NAME reserved reserved MFSDF (x) MFSDF-441 PLLFRAC-H PLLFRAC-441-H PLLFRAC-L PLLFRAC-441-L PLLCTRL VALUE 18 3 15 16 169 49 42 60 161
Table 7: PLL Configuration Sequence For 14.31818MHz Input Clock 256 Oversapling Rathio
REGISTER ADDRESS 6 11 97 80 101 82 100 81 5 NAME reserved reserved MFSDF (x) MFSDF-441 PLLFRAC-H PLLFRAC-441-H PLLFRAC-L PLLFRAC-441-L PLLCTRL VALUE 12 3 15 16 187 103 58 119 161
Table 6: PLL Configuration Sequence For 10MHz Input Clock 384 Oversapling Rathio
REGISTER ADDRESS 6 11 97 80 101 82 100 81 5 NAME reserved reserved MFSDF (x) MFSDF-441 PLLFRAC-H PLLFRAC-441-H PLLFRAC-L PLLFRAC-441-L PLLCTRL VALUE 17 3 9 10 110 160 152 186 161
Table 8: PLL Configuration Sequence For 14.31818MHz Input Clock 384 Oversapling Rathio
REGISTER ADDRESS 6 11 97 80 101 82 100 81 5 NAME reserved reserved MFSDF (x) MFSDF-441 PLLFRAC-H PLLFRAC-441-H PLLFRAC-L PLLFRAC-441-L PLLCTRL VALUE 11 3 6 7 3 157 211 157 161
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STA015-STA015B-STA015T
Table 9: PLL Configuration Sequence For 14.31818MHz Input Clock 512 Oversapling Rathio
REGISTER ADDRESS 6 11 97 80 101 82 100 81 5 NAME reserved reserved MFSDF (x) MFSDF-441 PLLFRAC-H PLLFRAC-441-H PLLFRAC-L PLLFRAC-441-L PLLCTRL VALUE 11 3 6 7 3 157 211 157 161
Table 11: PLL Configuration Sequence For 14.7456MHz Input Clock 384 Oversapling Rathio
REGISTER ADDRESS 6 11 97 80 101 82 100 81 5 NAME reserved reserved MFSDF (x) MFSDF-441 PLLFRAC-H PLLFRAC-441-H PLLFRAC-L PLLFRAC-441-L PLLCTRL VALUE 10 3 8 9 64 124 0 0 161
Table 10: PLL Configuration Sequence For 14.7456MHz Input Clock 256 Oversapling Rathio
REGISTER ADDRESS 6 11 97 80 101 82 100 81 5 NAME reserved reserved MFSDF (x) MFSDF-441 PLLFRAC-H PLLFRAC-441-H PLLFRAC-L PLLFRAC-441-L PLLCTRL VALUE 12 3 15 16 85 4 85 0 161
Table 12: PLL Configuration Sequence For 14.7456MHz Input Clock 512 Oversapling Rathio
REGISTER ADDRESS 6 11 97 80 101 82 100 81 5 NAME reserved reserved MFSDF (x) MFSDF-441 PLLFRAC-H PLLFRAC-441-H PLLFRAC-L PLLFRAC-441-L PLLCTRL VALUE 9 2 5 6 0 184 0 0 161
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5.6. STA015 CONFIGURATION FILE FORMAT The STA015 Configuration File is an ASCII format. An example of the file format is the following: 58 1 42 4 128 15 ............ It is a sequence of rows and each one can be interpreted as an I2C command. The first part of the row is the I 2C address (register) and the second one is the I2C data (value). To download the STA015 configuration file into the device, a sequence of write operation to STA015 I2C interface must be performed. The following program describes the I2C routine to be implemented for the configuration driver:
42
4
I2C REGISTER VALUE I2C SUB-ADDRESS
D98AU976
STA015 Configuration Code (pseudo code) download cfg - file { fopen (cfg_file); fp:=1;
/*set file pointer to first row */
do { I2C_start_cond; I2C_write_dev_addr; I2C_write_subaddress(fp); I2C_write_data (fp); I2C_stop_cond; fp++; } while (!EDF) }
/* generate I2C start condition for STA015 device address */ /* write STA015 device address */ /* write subaddress */ /* write data */ /* generate I 2C stop condition */ /* update pointer to new file row */ /* repeat until End of File /* End routine */ */
Note:1 STA015 is a device based on an integrated DSP core. Some of the I2C registers default values are loaded after an internal DSP boot operation. The bootstrap time is 60 micro second. Only after this time lenght, the data in the register can be considered stable. Note 2: Refer also to the application note AN1250
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DIM. MIN. A a1 b b1 C c1 D E e e3 F L S 7.4 0.4 17.7 10 0.1 0.35 0.23
mm TYP. MAX. 2.65 0.3 0.49 0.32 0.5 45 (typ.) 18.1 10.65 1.27 16.51 7.6 1.27 0.291 0.016 0.697 0.394 0.004 0.014 0.009 MIN.
inch TYP. MAX. 0.104 0.012 0.019 0.013 0.020
OUTLINE AND MECHANICAL DATA
0.713 0.419 0.050 0.65 0.299 0.050
SO28
8 (max.)
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STA015-STA015B-STA015T
DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.45 0.05 1.35 0.30 0.09
mm TYP. MAX. 1.60 0.15 1.40 0.37 1.45 0.45 0.20 12.00 10.00 8.00 0.80 12.00 10.00 8.00 0.60 1.00 0.75 0.018 0.002 0.053 0.012 0.004 MIN.
inch TYP. MAX. 0.063 0.006 0.055 0.014 0.057 0.018 0.008 0.472 0.394 0.315 0.031 0.472 0.394 0.315 0.024 0.039 0.030
OUTLINE AND MECHANICAL DATA
TQFP44 (10 x 10)
0(min.), 3.5(typ.), 7(max.)
D D1 A1
33 34 23 22
0.10mm .004 Seating Plane
A A2
E1
B
44 1 11
12
E
B
e
L
C
K
TQFP4410
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STA015-STA015B-STA015T
mm DIM. MIN. A A1 A2 b D D1 e E E1 f 0.350 0.400 1.100 0.500 8.000 5.600 0.800 8.000 5.600 1.200 TYP. MAX. 1.700 0.450 0.014 MIN.
inch TYP. MAX. 0.067 0.016 0.043 0.20 0.315 0.220 0.031 0.315 0.220 0.047 0.018
OUTLINE AND MECHANICAL DATA
Body: 8 x 8 x 1.7mm
LFBGA64
BALL 1 IDENTIFICATION A D1 8 A B C D E F G H b (64 PLACES) e A2 E1 7 6 5 4 3 2 1 f f
0.15
A1
D
E
LFBGA64M
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STA015-STA015B-STA015T
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